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data sheet 0 8 .9 5 mi c r o c omp u ter componen t s sab 80515 / sab 80535 8-bit single-chip microcontroller family
sab 80515 / 80535 data sheet revision history: current version: 08.95 previous version: 09.89, 11.92 page subjects (changes since last revision) 1, 2, 27, 29, 30 29 36 C 40 to + 110 ?c version deleted; note: only on request ... added t c and v int error modified header of table (16 mhz) corrected edition 08.95 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1995. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express writ- ten approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
semiconductor group 3 8.95 high-performance 8-bit single chip microcontroller sab 80515/80535 preliminary sab 80515 microcontroller with factory mask-programmable rom sab 80535 microcontroller for external rom l 8 k 8 rom (sab 80c515 only) l 256 8 ram l six 8-bit i/o ports, one 8-bit input port for analog signals l three 16-bit timer/counters l highly flexible reload, capture, compare capabilities l full-duplex serial channel l twelve interrupt vectors, four priority levels l 8-bit a/d converter with 8 multiplexed inputs and programmable internal reference voltages l 16-bit watchdog timer l v pd provides standby current for 40 bytes of ram l boolean processo l 256-bit-addressable locations l most instructions execute in 1 m s (750 ns) l 4 m s (3 m s) multiply and divide l external memory expandable up to 128 kbytes l backwardly compatible with sab 8051 l two temperature ranges available: 0 to 70 ?c C 40 to 85 ?c (t40/85) the sab 80515/80535 is a powerful member of the siemens sab 8051 family of 8-bit micro- controllers. it is fabricated in + 5 v n-channel, silicon-gate siemens mymos technology. the sab 80515/80535 is a stand-alone, high-performance single-chip microcontroller based on the sab 8051 architecture. while maintaining all the sab 8051 operating characteristics, the sab 80515/80535 incorporates several enhancements which significantly increase design flexibility and overall system performance. the sab 80535 is identical with the sab 80515 except that it lacks the on-chip program me- mory. the sab 80515/80535 is supplied in a 68-pin plastic leaded chip carrier package (p-lcc-68).
sab 80515/80535 semiconductor group 4 note: extended temperature range C 40 to 110 ?c on request ordering information type ordering code package description 8-bit cmos microcontroller sab 80515-n q 67120-c211 p-lcc-68 with mask-programmable rom sab 80535-n q 67120-c241 p-lcc-68 for external memory sab 80515-n-t40/85 q 67120-c210 p-lcc-68 with mask-programmable rom sab 80535-n-40/85 q 67120-c240 p-lcc-68 for external memory
sab 80515/80535 semiconductor group 5 logic symbol pin configuration (p-lcc-68)
sab 80515/80535 semiconductor group 6 pin definitions and functions symbol pin input (i) output (o) function p4.0-p4.7 1-3, 5-9 i/o port 4 is an 8-bit quasi-bidirectional i/o port . port 4 can sink/source 4 ls-ttl loads. v pd 4 i power down supply. if v pd is held within its specs while v cc drops below specs, v pd will provide standby power to 40 byte of the internal ram. when v pd is low, the rams current is drawn from v cc . reset 10 i a low level on this pin for the duration of two machine cycles while the oscillator is running resets the sab 80c515. a small internal pullup resistor permits power-on reset using only a capacitor connected to v ss v aref 11 reference voltage for the a/d converter v agnd 12 reference ground for the a/d converter an7-an0 13-20 i multiplexed analog inputs
sab 80515/80535 semiconductor group 7 pin definitions and functions (contd) symbol pin input (i) output (o) function p3.0-p3.7 21-28 i/o port 3 is an 8-bit bidirectional i/o. it also contains the in- terrupt, timer, serial port and external memory strobe pins that are used by various options. the output latch corresponding to a secondary function must be pro- grammed to a one (1) for that function to operate. port 3 can sink/source 4 ls-ttl loads.the secondary func- tions are assigned to the pins of port 3, as follows: Cr d (p3.0): serial ports receiver data input (asynchronous) or data input/output (synchronous) Ct d (p3.1): serial ports transmitter data output (asynchronous) or clock output (synchronous) C int0(p3.2): interrupt 0 input/timer 0 gate control input C int1(p3.3): interrupt 1 input/timer 1 gate control input C t0 (p3.4): counter 0 input C t1 (p3.5): counter 1 input C wr(p3.6): the write control signal latches the data byte from port 0 into the external data memory C rd (p3.7): the read control signal enables the external data memory to port 0
sab 80515/80535 semiconductor group 8 pin definitions and functions (contd) symbol pin input (i) output (o) function p1.7 - p1.0 29 - 36 i/o port 1 is an 8-bit bidirectional i/o port .it is used for the low-order address byte during program verification. it also contains the interrupt, timer, clock, capture and compare pins that are used by various options. the out- put latch must be programmed to a one (1) for that func- tion to operate (except when used for the compare func- tions). the secondary functions are assigned to the port 1 pins as follows: C int3/cc0 (p1.0): interrupt 3 input / compare 0 output / capture 0 input C int4/cc1 (p1.1): interrupt 4 input / compare 1 output / capture 1 input C int5/cc2 (p1.2): interrupt 5 input / compare 2 output / capture 2 input C int6/cc3 (p1.3): interrupt 6 input / compare 3 output / capture 3 input C int2(p1.4): interrupt 2 input C t2ex (p1.5): timer 2 external reload trigger input C clkout (p1.6): system clock output C t2 (p1.7): counter 2 input v bb 37 substrate pin. must be connected to v ss through a capacitor (47 to 100 nf) for proper operation of the a/d converter. xtal2 39 C xtal2 is the output from the oscillators amplifier.input to the internal timing circuitry. a crystal, ceramic resona- tor, or external source can be used. xtal1 40 C xtal1 is the input to the oscillators high gain amplifier. required when a crystal or ceramic resonator is used. connect to v ss when external source is used on xtal2.
sab 80515/80535 semiconductor group 9 pin definitions and functions (contd) symbol pin input (i) output (o) function p2.0-p2.7 41- 48 i/o port 2 is an 8-bit quasi-bidirectional i/o port. it also emits the high-order address byte when accessing ex- ternal memory. it is used for the high-order address and the control signals during program verification. port 2 can sink/source 4 ls-ttl loads. psen 49 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscil- lator periods except during external data memory ac- cesses. remains high during internal program executi- on. ale 50 o provides address latch enable output used for latching the address into external memory during normal opera- tion. it is activated every six oscillator periods except du- ring an external data memory access. ea 51 i when held at a ttl high level, the sab 80515 executes instructions from the internal rom when the pc is less than 8192. when held at a ttl low level, the sab 80515 fetches all instructions from external program memory. for the sab 80535 this pin must be tied low. p0.0-p0.7 52-59 i/o port 0 is an 8-bit open-drain bidirectional i/o port. it is also the multiplexed low-order address and data bus when using external memory. it is used for data output during program verification. port 0 can sink/source 8 ls-ttl loads. p5.7-p5.0 60-67 i/o port 5 is an 8-bit quasi-bidirectional i/o port. port 5 can sink/source 4 ls-ttl loads. v cc 68 power supply (+ 5 v power supply during normal operation and program verification) v ss 38 ground (0 v)
sab 80515/80535 semiconductor group 10 figure 1 block diagram
sab 80515/80535 semiconductor group 11 functional description the architecture of the sab 80515 is based on the sab 8051 microcontroller family. the fol- lowing features of the sab 80515 are fully compatible with the sab 8051 features: C instruction set C external memory expansion interface (port 0 and port 2) C full-duplex serial port C timer/counter 0 and 1 C alternate functions on port 3 C the lower 128 bytes of internal ram and the lower 4 kbytes of internal rom the sab 80515 additionally contains 128 bytes of internal ram and 4 kbytes of internal rom, which results in a total of 256 bytes of ram and 8 kbytes of rom on chip. the sab 80515 has a new 16-bit timer/counter with a 2:1 prescaler, reload mode, compare and capture capability. it also contains a 16-bit watchdog timer, an 8-bit a/d converter with pro- grammable reference voltages, two additional quasi-bidirectional 8-bit ports, one 8-bit input port for analog signals, and a programmable clock output ( f osc /12). furthermore, the sab 80515 has a powerful interrupt structure with 12 vectors and 4 program- mable priority levels. figure 1 shows a block diagram of the sab 80515. cpu the sab 80515 is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions execute in 1.0 m s. memory organization the sab 80515 manipulates operands in the four memory address spaces described in the fol- lowing. (figure 2 illustrates the memory address spaces of the sab 80515).
sab 80515/80535 semiconductor group 12 figure 2 memory address spaces
sab 80515/80535 semiconductor group 13 program memory the sab 80515 has 8 kbyte of on-chip rom, while the sab 80535 has no internal rom. the program memory can be externally expanded up to 64 kbytes. if the ea pin is held high, the sab 80515 executes out of internal rom unless the address exceeds 1fff h . locations 2000 h through 0ffff h are then fetched from the external program memory. if the ea pin is held low, the sab 80515 fetches all instructions from the external program memory. since the sab 80535 has no internal rom, pin ea must be tied low when using this component. data memory the data memory address space consists of an internal and an external memory space. the internal data memory is divided into three physically separate and distinct blocks: the lower 128 bytes of ram, the upper 128 bytes of ram, and the 128-byte special function register (sfr) area. while the upper 128 bytes of data memory and the sfr area share the same address locations, they are accessed through different addressing modes. the lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of ram can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy loca- tions 0 through 1f h in the lower ram area. the next 16 bytes, locations 20 h through 2f h , con- tain 128 directly addressable bit locations. the stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. the external data memory can be expanded up to 64 kbytes and can be accessed by instruc- tions that use a 16-bit or an 8-bit address.
sab 80515/80535 semiconductor group 14 special function registers all registers, except the program counter and the four 8-register banks, reside in the special function register area. the 41 special function registers (sfrs) include arithmetic registers, pointers, and registers that provide an interface between the cpu and the on-chip peripheral functions. there are also 128 directly addressable bits within the sfr area. the special function registers are listed in the following table: in table 1 they are organized in numeric order of their addresses. in table 2 they are organized in groups which refer to the functional blocks of the sab 80515/80535. table 1 special function register address register contents after reset address register contents after reset 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h p0 1) sp dpl dph reserved reserved reserved pcon 0ff h 07 h 00 h 00 h xx h 2) xx h 2) xx h 2) 000x 0000 b 2) 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h scon 1) sbuf reserved reserved reserved reserved reserved reserved 00 h xxxx xxxx b xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h tcon 1) tmod tl0 tl1 th0 th1 reserved reserved 00 h 00 h 00 h 00 h 00 h 00 h xx h 2) xx h 2) a0 h a1 h a2 h a3 h a4 h a5 h a6 h a7 h p2 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h p1 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) a8 h a9 h aa h ab h ac h ad h ae h af h ien0 1) ip0 reserved reserved reserved reserved reserved reserved 00 h x000 0000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 1) bit-addressable special function register 2) x means that the value is indeterminate and the location is reserved
sab 80515/80535 semiconductor group 15 table 1 special function register (contd) address register contents after reset address register contents after reset b0 h b1 h b2 h b3 h b4 h b5 h b6 h b7 h p3 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2 ) xx h 2 ) xx h 2 ) xx h 2 ) xx h 2 ) xx h 2 ) xx h 2 ) d0 h d1 h d2 h d3 h d4 h d5 h d6 h d7 h psw 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) b8 h b9 h ba h bb h bc h bd h be h bf h ien1 1) ip1 reserved reserved reserved reserved reserved reserved 00 h xx00 0000 b 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2 d8 h d9 h da h db h dc h dd h de h df h adcon addat dapr p6 reserved reserved reserved reserved 00x0 0000 b 2) 00 h 00 h xx h 2) xx h 2) xx h 2) xx h 2) c0 h c1 h c2 h c3 h c4 h c5 h c6 h c7 h ircon 1) ccen ccl1 cch1 ccl2 cch2 ccl3 cch3 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h e0 h e1 h e2 h e3 h e4 h e5 h e6 h e7 h acc 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) c8 h c9 h ca h cb h cc h cd h ce h cf h t2con 1) reserved crcl crch tl2 th2 reserved reserved 00 h xx h 2) 00 h 00 h 00 h 00 h xx h 2) xx h 2) e8 h e9 h ea h eb h ec h ed h ee h ef h p4 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 1) bit-addressable special function register 2) x means that the value is indeterminate and the location is reserved
sab 80515/80535 semiconductor group 16 f0 h f1 h f2 h f3 h f4 h f5 h f6 h f7 h b 1) reserved reserved reserved reserved reserved reserved reserved 00 h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) f8 h f9 h fa h fb h fc h fd h fe h ff h p5 1) reserved reserved reserved reserved reserved reserved reserved 0ff h xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) xx h 2) 1) bit-addressable special function register 2) x means that the value is indeterminate and the location is reserved table 1 special function register (contd) address register contents after reset address register contents after reset
sab 80515/80535 semiconductor group 17 table 2 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl psw sp accumululator b-register data pointer, high byte data pointer, low byte program status word register stack pointer 0e0 h 1) 0f0 h 1) 083 h 082 h 0d0 h 1) 081 h 00 h 00 h 00 h 00 h 00 h 07 h a/d- converter adcon 2) addat dapr a/d converter control register a/d converter data register a/d converter program register 0d8 h 1) 09d h 0da h 00x0 0000 b 3 ) 00 h 00 h ) interrupt system ien0 2) ien1 2) ip0 2) ip1 ircon tcon 2) t2con 2) interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 interrupt priority register 1 interrupt request control register timer control register timer 2 control register 0a8 h 1) 0b8 h 1) 0a9 h 0b9 h 0c0 h 1) 88 h 1) 0c8 h 1 00 h 00 h x000 0000 b 3) xx00 0000 b 3) 00 h 00 h 00 h compare/ capture- unit compare/ capture- unit (ccu) (contd) (ccu) ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con 2) comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2. low byte comp./capture reg. 3, low byte com./rel./capt. reg. high byte com./rel./capt. reg. low byte timer 2, high byte timer 2, low byte timer 2 control register 1 ) 0c1 h 0c3 h 0c5 h 0c7 h 0c2 h 0c4 h 0c6 h 0cb h 0ca h 0cd h 0cc h 0c8 h 1) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks 3) x means that the value is indeterminate
sab 80515/80535 semiconductor group 18 table 2 special function registers- functional blocks (contd) block symbol name address contents after reset ports p0 p1 p2 p3 p4 p5 p6 port 0 port 1 port 2 port 3 port 4 port 5 port 6, analog/digital input 80 h 1) 90 h 1) 0a0 h 1) 0b0 h 1) 0e8 h 1) 0f8 h 1) 0db h 0ff h 0ff h 0ff h 0ff h 0ff h 0ff h pow. sav. modes pcon 2 ) power control register 087 h 000x 0000 b 2) serial channels adcon 2) pcon 2) sbuf scon a/d converter control reg. power control register serial channel buffer reg. serial channel control reg. 0d8 h 1) 087 h 099 h 098 h 1) 00x0 0000 b 3) 000x 0000 b 3 ) xxxx xxxx b 3) 00 h timer 0/ timer 1 tcon 2) th0 th1 tl0 tl1 tmod timer control register timer 0. high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 0 88 h 1) 08c h 08d h 08a h 08b h 089 h 00 h 00 h 00 h 00 h 00 h 00 h watchdog ien0 2) ien1 2) ip0 2) interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 0a8 h 1) 0b8 h 1) 0a9 h 00 h 00 h x000 0000 b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is indeterminate and the location is reserved
sab 80515/80535 semiconductor group 19 serial port the serial port of the sab 80515 enables full duplex communication between microcontrollers or between microcontroller and peripheral devices. the serial port can operate in 4 modes: mode 0: shift register mode. serial data enters and exits through r d. t d outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed at 1/12 of the oscillator frequency. mode 1: 10 bits are transmitted (through r d) or received (through t d): a start bit (0), 8 data bits (lsb first), and a stop bit (1). the baud rate is variable. mode 2: 11 bits are transmitted (through r d) or received (through t d): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). the baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. mode 3: 11 bits are transmitted (through t d) or received (through r d): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). mode 3 is identical to mode 2 except for the baud rate. the baud rate in mode 3 is variable. the variable baud rates in modes 1 and 3 can be generated by timer 1 or an internal baud rate generator. a/d converter the 8-bit a/d converter of the sab 80515 has eight multiplexed analog inputs (port 6) and uses the successive approximation method. it takes 5 machine cycles to sample an analog signal (during this sample time the input signal should be held constant); the total conversion time (including sample time) is 15 machine cyc- les (15 m s at 12 mhz oscillator frequency). conversion can be programmed to be single or continuous; at the end of a conversion an interrupt can be generated. a unique feature is the capability of internal reference voltage programming. the internal refe- rence voltages v intaref and v intagnd for the a/d converter both are programmable to one of 16 steps with respect to the external reference voltages. this feature permits a conversion with a smaller internal reference voltage range to gain a higher resolution. in addition, the internal reference voltages can easily be adapted by software to the desired analog input voltage range. figure 3 shows a block diagram of the a/d converter.
sab 80515/80535 semiconductor group 20 figure 3 block diagram of the a/d converter
sab 80515/80535 semiconductor group 21 timer/counters the sab 80515 contains three 16-bit timer/counters which are useful in many applications for timing and counting. the input clock for each timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation (maximum count rate is 1/24 of the oscillator frequency). C timer/counter 0 and 1 these timer/counters can operate in four modes: mode 0: 8-bit timer/counter with 32:1 prescaler mode 1: 16-bit timer/counter mode 2: 8-bit timer/counter with 8-bit auto-reload mode 3: timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; timer/counter 1 in this mode holds its count. external inputs int0 and int1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. C timer/counter 2 timer/counter 2 of the sab 80515 is a 16-bit timer/counter with several additional features. it offers a 2:1 prescaler, a selectable gate function, and compare, capture and reload functions. corresponding to the 16-bit timer register there are four 16-bit capture/compare registers, one of them can be used to perform a 16-bit reload on a timer overflow or external event. each of these registers corresponds to a pin of port 1 for capture input/compare output. figure 4 shows a block diagram of the timer/counter 2. reload a 16-bit reload can be performed with the 16-bit crc register, which is a concatenation of the 8-bit registers crcl and crch. there are two modes from which to select: mode 0: reload is caused by a timer 2 overflow (auto-reload). mode 1: reload is caused in response to a negative transition at pin t2ex (p1.5), which can also request an interrupt. capture this feature permits saving the actual timer/counter contents into a selected register upon an external event or a software write operation. two modes are provided to latch the current 16- bit value in timer 2 registers into a dedicated capture register: mode 0: capture is performed in response to a transition at the corresponding port 1 pins cc0 to cc3. mode 1: write operation into the low-order byte of the dedicated capture register causes the timer 2 contents to be latched into this register.
sab 80515/80535 semiconductor group 22 compare in the compare mode, the 16-bit values stored in the dedicated compare registers are compa- red to the contents of the timer 2 registers. if the count value in the timer 2 registers matches one of the stored values, an appropriate output signal is generated and an interrupt is requ- ested. two compare modes are provided: mode 0: upon a match the output signal changes from low to high. it goes back to a low level when timer 2 overflows. mode 1: the transition of the output signal can be determined by software. a timer 2 overflow causes no output change.
sab 80515/80535 semiconductor group 23 figure 4 block diagram of timer/counter 2
sab 80515/80535 semiconductor group 24 interrupt structure the sab 80515 has 12 interrupt vectors with the following vector addresses and request flags: each interrupt vector can be individually enabled/disabled. the minimum response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles. figure 5 shows the interrupt request sources. external interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable) at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition. the external interrupts 3 to 6 are combined with the cor- responding alternate functions compare (output) and capture (input) on port 1. for programming of the priority levels the interrupt vectors are combined to pairs. each pair can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register ip0 and one in ip1. figure 6 shows the priority level structure. table 3 interrupt sources and vectors source (request flags) vector address vector ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 iadc iex2 iex3 iex4 iex5 iex6 0003 h 000b h 0013 h 001b h 0023 h 002b h 0043 h 004b h 0053 h 005b h 0063 h 006b h external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt a/d converter interrupt external interrupt 2 external interrupt 3 external interrupt 4 external interrupt 5 external interrupt 6
sab 80515/80535 semiconductor group 25 figure 5 interrupt request sources
sab 80515/80535 semiconductor group 26 figure 6 priority level structure
sab 80515/80535 semiconductor group 27 i/o ports the sab 80515 has six 8-bit i/o ports and one 8-bit input port. port 0 is an open-drain bidi- rectional i/o port, while ports 1 to 5 are quasi-bidirectional i/o ports with internal pull-up resi- stors. that means, when configured as inputs, ports 1 to 5 will be pulled high and will source current when externally pulled low. port 0 will float when configured as input. port 0 and port 2 can be used to expand the program and data memory externally. during an access to external memory, port 0 emits the low-order address byte and reads/writes the data byte, while port 2 emits the high-order address byte. in this function, port 0 is not an open-drain port, but uses a strong internal pullup fet. ports 1 and 3 are provided for several alternate functions, as listed below: the input port an0-an7 is used for analog input signals to the a/d converter. port symbol function p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 int3/cc0 int4/cc1 int5/cc2 int6/cc3 int2 t2ex clkout t2 rxd txd int0 int1 t0 t1 wr rd external interrupt 3 input, compare 0 output, capture 0 input external interrupt 4 input, compare 1 output, capture 1 input external interrupt 5 input, compare 2 output, capture 2 input external interrupt 6 input, compare 3 output, capture 3 input external interrupt 2 input timer 2 external reload trigger input system clock output timer 2 external counter input serial ports receiver data input (asynchronous) or data input/output (synchronous) serial ports transmitter data output (asynchronous) or clock output (synchronous) external interrupt 0 input, timer 0 gate control external interrupt 1 input, timer 1 gate control timer 0 external counter input timer 1 external counter input external data memory write strobe external data memory read strobe
sab 80515/80535 semiconductor group 28 watchdog timer this feature is provided as a means of graceful recovery from a software upset. after an exter- nal reset, the watchdog timer is cleared and stopped. it can be started and cleared by software, but it cannot be stopped. if the software fails to clear the watchdog timer at least every 65532 machine cycles (about 65 ms if a 12 mhz oscillator frequency is used), an internal hardware reset will be initiated. the reset cause (external reset or reset caused by the watchdog) can be examined by soft- ware. to clear the watchdog, two bits in two different special function registers must be set by two consecutive instructions (bits ien0.6 and ien1.6). this is done to prevent the watchdog from being cleared by unexpected opcodes. instruction set summary the sab 80515/80535 has the same instruction set as the industry standard 8051 microcontroller. a pocket guide is available which contains the complete instruction set in functional and hexadecimal order. furtheron it provides helpful information about special function registers, interrupt vectors and assembler directives. literature information title ordering no. microcontroller family sab 8051 pocket guide b158-b6599 - x - x - 7600
sab 80515/80535 semiconductor group 29 absolute maximum ratings ambient temperature under bias sab 80515/80535 ............................................................................................. 0 to 70 c sab 80515/80535-t40/85................................................................................. C 40 to 85 c storage temperature ......................................................................................... C 65 to 150 c voltage on any pins with respect to ground ( v ss ) ............................................. C 0.5 v to 7 v power dissipation .............................................................................................. 2 w note stresses above those listed under "absolute maximum ratings" may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics v cc = 5 v 10 %; v ss = 0 v t a = 0 to 70 c for the sab 80515/80535 t a = C 40 to 85 c for the sab 80515/80535-t40/85 t a = C 40 to110 c for the sab 80515/80535-t40/110 parameter symbol limit values unit test condition min. max. input low voltage v il C 0.5 0.8 v C input high voltage ) (except reset, xtal2 v ih 2. 0 v cc C 0.5 vC input high voltage to xtal2 v ih1 2.5 v cc + 0.5 v xtal1 to v ss input high voltage to reset v ih2 3.0 C v C power down voltage v pd 3 5.5 v v cc = 0 v output low voltage ports 1, 2, 3, 4, 5 v ol C 0.45 v i ol = 1.6 ma 1) output low voltage port 0, ale, psen v ol1 C 0.45 v i ol = 3.2 ma 1) output high voltage ports 1, 2, 3, 4, 5 v oh 2.4 C v i oh = C 80 m a output high voltage port 0, ale, psen v oh1 2.4 C v i oh = C 400 m a 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and ports 1,3,4,5. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-0 transitions during bus operation.
sab 80515/80535 semiconductor group 30 dc characteristics (contd) parameter symbol limit values unit test condition min. max. logic 0 input current ports 1, 2, 3, 4, 5 i il C C 800 m a v il = 0.45 v logic 0 input current xtal2 i il2 C C 2.5 ma xtal1 = v ss v il = 0.45 v input low current to reset for reset i il3 C C 500 m a v il = 0.45 v input leakage current to port 0, ea an0 - an7 i li C 10 m a 0 v < v in < v cc power supply current: ) sab 80515/80535 sab 80515/80535-t40/85 sab 80515/80535-t40/110 i cc i cc i cc C C C 210 230 230 ma ma ma all outputs disconnected power-down current i pd C3ma v cc = 0 v capacitance of i/o buffer c io C10pf f c =1 mhz 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and ports 1,3,4,5. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-0 transitions during bus operation.
sab 80515/80535 semiconductor group 31 a/d converter characteristics v cc = 5 v 10 %; v ss = 0 v; v aref = v cc 5 %; v agnd = v ss 0.2 v; v intaref C v intagnd 3 1 v; t a = 0 to + 70 ?c for sab 80515/80535 t a = C 40 to + 85 ?c for sab 80515/80535 - t40/85 parameter symbol limit values unit test condition min. typ. max. analog input voltage v ainput v agnd - 0.2 C v aref + 0.2 vC analog input capacitance c i C25Cpf 1) load time t l CC2 t cy m sC sample time (incl. load time) t s CC5 t cy m sC conversion time (including sample time) t c CC13 t cy m sC differential non-linearity integral non-linearity offset error gain error total unadjusted error dnle inle tue C 1/2 1/2 1/2 1/2 1 1 1 1 1 2 lsb lsb lsb lsb lsb v intaref = v aref = v cc v intagnd = v agnd = v ss 2) v aref supply current i re f CC5ma 2) internal reference error v intrefer C 5 30 mv 2) 1) the internal resistance of the analog source must be low enough to assure full loading of the sample capaci- tance ( c i )during load time ( t l ) . after charging of the internal capacitance ( c i ) in the load time ( t l ) the analog input must be held constant for the rest of the sample time ( t s ). 2) the differential impedance r d of the analog reference voltage source must be less than 1 k w at reference supply voltage.
sab 80515/80535 semiconductor group 32 ac characteristics v cc = 5 v 10 %; v ss = 0 v ; ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) t a = 0 to + 70 ?c; for sab 80515/80535 t a = C 40 to + 85 ?c; for sab 80515/80535 - 40/85 parameter symbol limit values unit 12 mhz clock variable clock 1/ t clcl = 1.2 mhz to 12 mhz min max. min. max. program memory characteristics cycle time t cy 1000 C 12 t c lcl Cns ale pulse width t lhll 127 C 2 t c lcl C 40 C ns address setup to ale t avll 53 C t c lcl C 30 C ns address hold after ale t llax1 48 C t c lcl C 35 C ns ale to valid instruction in t lliv C 233 C 4 t c lcl C 100 ns ale to psen t llpl 58 C t c lcl C 25 C ns psen pulse width t plph 215 3 t c lcl C 35 C ns psen to valid instruction in t pliv C 150 C 3 t c lcl C100 ns input instruction hold after psen t pxix 0C0 C ns input instruction float after psen t pxiz *) C63 C t c lcl C 20 ns address valid after psen t pxav *) 75 C t c lcl C 8 C ns address to valid instruction in t a viv C 302 C 5 t c lcl C 115 ns address float to psen t a zpl 0C0 C ns *) interfacing the sab 805156 to devices with float times up to 75 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers.
sab 80515/80535 semiconductor group 33 parameter symbol limit values unit 12 mhz clock variable clock 1/ t clcl = 1.2 mhz to 12 mhz min max. min. max. external data memory characteristics rd pulse width t rlrh 400 C 6 t clcl C 100 C ns wr pulse width t wlwh 400 C 6 t clcl C 100 C ns address hold after ale t llax2 132 C 2 t clcl C 35 C ns rd to valid data in t rldv C 252 C 5 t clcl C 165 ns data hold after rd t rhdx 0C 0 ns data float after rd t rhdz C97 C 2 t clcl C 70 ns ale to valid data in t lldv C 517 C 8 t clcl C 150 ns address to valid data in t avdv C 585 C 9 t nclcl C 165 ns ale to wr or rd t llwl 200 300 3 t clcl C 50 3 t clcl + 50 ns address to wr or rd t avwl 203 C4 clcl C 130 C ns wr or rd high to ale high t whlh 43 123 t clcl C 40 t clcl + 40 ns data valid to wr transition t qvwx 33 C t clcl C 50 C ns data setup before wr t qvwh 433 C 7 t clcl C 150 C ns data hold after wr t whqx 33 C t clcl C 50 C ns address float after rd t rlaz C0 C 0ns
sab 80515/80535 semiconductor group 34 waveforms program memory read cycle
sab 80515/80535 semiconductor group 35 data memory read cycle recommended oscillator circuits
sab 80515/80535 semiconductor group 36 ac characteristics (contd) external clock cycle parameter symbol limit values unit variable clock frequ. = 1.2 mhz to 12 mhz min. max. external clock drive xtal2 oscillator period t clcl 83.3 833.3 ns high time t chcx 20 t clcl C t clcx ns low time t clcx 20 t clcl C t chcx ns rise time t clch C 20 ns fall time t chcl C 20 ns oscillator period t clcl 83.3 833.3 ns
sab 80515/80535 semiconductor group 37 a.c. testing input, output, float waveforms a.c. testing inputs are driven at 2.4 v for a logic "1" and at 0.45 v for a logic "0". timing measurements are made at 2.0 v for a logic "1" and at 0.8 v for a logic "0". for timing purposes, the float state is defined as the point at which a p0 pin sinks 3.2 ma or sources 400 m a at the voltage test levels.
sab 80515/80535 semiconductor group 38 system clock timing ac characteristics (contd) parameter symbol limit values unit 12 mhz clock variable clock 1/ t clcl = 1.2 mhz to 12 mhz min. max. min. max. system clock timing ale to clkout t llsh 543 C 7 t clcl C 40 C ns clkout high time t shsl 127 C 2 t clcl C 40 C ns clkout low time t slsh 793 C 10 t clcl C 40 C ns clkout low to ale high t sllh 43 123 t clcl C 40 t clcl + 40 ns
sab 80515/80535 semiconductor group 39 rom verification characteristics t a = 25 ?c 5 ?c; v cc = 5 v 10 %; v ss = 0 v rom verification parameter symbol limit values unit min max. rom verification address to valid data t avqv C 48 t clcl1 ns enable to valid data t elqv C 48 t clcl1 ns data float after enable t ehoz 048 t clcl1 ns oscillator frequency 1/ t clcl 4 6 mhz address: p1.0-p1.7 = a0-a7 p2.0-p2.4 = a8-a12 data: port 0 = d0-d7 inputs: p2.5-p2.6, psen = v ss ale, ea = v ih reset = v il
sab 80515/80535 semiconductor group 40 package outlines plastic package, p-lcc-68 C smd (plastic leaded chip-carrier) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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